本篇文章介紹在STM32CubeIDE環境下使用HAL函式庫製作nRF24L01+驅動程式，使用IRQ pin，以GPIO interrupt處理nRF24L01的Data Sent, Data ready與max re-transmission interrupt。
#include <stdio.h>
#include "string.h"
#include "main.h"
#include "nRF24L01.h"
// SPI Defines
static SPI_HandleTypeDef* nRF24_SPI;
static GPIO_TypeDef* nRF24_GPIO_CE_port=GPIOB;
static GPIO_TypeDef* nRF24_GPIO_CSn_port=GPIOB;
static GPIO_TypeDef* nRF24_GPIO_IRQ_port=GPIOB;
static uint16_t nRF24_GPIO_CE_pin=GPIO_PIN_6;
static uint16_t nRF24_GPIO_CSn_pin=GPIO_PIN_7;
static uint16_t nRF24_GPIO_IRQ_pin=GPIO_PIN_8;
static uint32_t nRF24_SPI_TIMEOUT=1000;
//nRF24_irq_callback_t nRF24_callback;
static uint8_t nRF24_data_buffer[64];
static void nRF24_standby_to_txrx_mode();
static void nRF24_standby_I();
static void nRF24_reset_REGISTER();
static void nRF24_spi_enable();
static void nRF24_spi_disable();
/*!
* \brief STM32 GPIO IRQ Callback
* nRF24L01 IRQ callback function
* \param gpio: gpio number
*/
void HAL_GPIO_EXTI_Callback(uint16_t gpio) {
uint8_t status;
uint8_t event_type;
uint16_t data_src;
uint8_t width=0;
memset(nRF24_data_buffer,0, 32);
if (gpio == nRF24_GPIO_IRQ_pin) {
nRF24_status(&status);
data_src = (status & 0x0E) >> 1;
if ((status & 0x40) >> EVENT_RX_DR) { // RX_DR
event_type = EVENT_RX_DR;
if (nRF24_get_RX_payload_width(&width) == HAL_OK) {
if (width > 32) { // in nRF24L01+ product specification
printf("...in driver width > 32 datapipe:%d:%d\n", data_src, width);
nRF24_standby_I();
nRF24_flush_rx(); //
nRF24_standby_to_txrx_mode();
}
else {
nRF24_read_payload(nRF24_data_buffer, width);
nRF24_irq_callback(event_type, data_src, nRF24_data_buffer, width);
}
nRF24_clear_RX_DR();
}
}
if ((status & 0x20) >> EVENT_TX_DS) { // TX_DS
event_type = EVENT_TX_DS;
nRF24_irq_callback(event_type, data_src, nRF24_data_buffer, 0);
nRF24_clear_TX_DS();
}
if ((status & 0x10) >> EVENT_MAX_RT) { // MAX_RT
event_type = EVENT_MAX_RT;
nRF24_irq_callback(event_type, data_src, nRF24_data_buffer, 0);
nRF24_clear_MAX_RT();
}
} else {
event_type = EVENT_GPIO_IRQ; // STM32 gpio irq except nRF24L01 IRQ
nRF24_irq_callback(event_type, gpio, nRF24_data_buffer, width);
}
}
/*!
* \brief set nRF24L01 PWR_UP in CONFIG register
*/
static void nRF24_config_PWR_UP() {
uint8_t ret;
uint8_t mode;
ret = nRF24_read_REGISTER(CONFIG, &mode,1);
if (ret == HAL_OK) {
mode |= (0x02);
ret = nRF24_write_REGISTER(CONFIG, &mode,1);
}
}
/*!
* \brief enable CE, set CE high
*/
static void nRF24_enable_CE() {
//gpio_put(nRF24_CE, enable);
HAL_GPIO_WritePin(nRF24_GPIO_CE_port, nRF24_GPIO_CE_pin, GPIO_PIN_SET);
}
/*!
* \brief enable CE, set CE low
*/
static void nRF24_disable_CE() {
//gpio_put(nRF24_CE, enable);
HAL_GPIO_WritePin(nRF24_GPIO_CE_port, nRF24_GPIO_CE_pin, GPIO_PIN_RESET);
}
static void nRF24_standby_I() {
nRF24_disable_CE();
}
/*!
* \brief nRF24L01 active FEATURE. nRF24L01+ does not need this function
*/
uint8_t nRF24_activate() {
uint8_t ret;
uint8_t status;
uint8_t value = 0x73;
uint8_t cmd = ACTIVATE;
nRF24_spi_enable();
//ret = spi_write_blocking(SPI_PORT, cmd, 2);
ret = HAL_SPI_TransmitReceive(nRF24_SPI, &cmd, &status, 1, nRF24_SPI_TIMEOUT);
if (ret == HAL_OK) {
ret = HAL_SPI_Transmit(nRF24_SPI, &value, 1, nRF24_SPI_TIMEOUT);
}
nRF24_spi_disable();
return ret;
}
/*!
* \brief 1. set SPI pin and initialize.
* 2.set nRF24L01 to standby-I mode
* \param spi SPI handle
* \param Csn_port GPIO port
* \param Csn_pin GPIO pin
* \param ce_port nRF24L01 CE GPIO port
* \param ce_pin nRF240L01 CE GPIO pin
* \param irq_port nRF24L01 IRQ GPIO port
* \param irq_pin nRF24L01 IRQ GPIO pin
*/
void nRF24_spi_init(SPI_HandleTypeDef* spi, GPIO_TypeDef* csn_port, uint32_t csn_pin, GPIO_TypeDef* ce_port, uint32_t ce_pin, GPIO_TypeDef* irq_port, uint32_t irq_pin) {
nRF24_SPI = spi;
nRF24_GPIO_CSn_port = csn_port;
nRF24_GPIO_CSn_pin = csn_pin;
nRF24_GPIO_CE_port = ce_port;
nRF24_GPIO_CE_pin = ce_pin;
nRF24_GPIO_IRQ_port = irq_port;
nRF24_GPIO_IRQ_pin = irq_pin;
nRF24_reset_REGISTER();
nRF24_config_PWR_UP();
//nRF24_activate(); //nRF24L01 Product Specification
nRF24_disable_CE(); //standby-I
HAL_Delay(1);
}
/*!
* \brief enable SPI, set CS LOW.
*/
void nRF24_spi_enable() {
HAL_GPIO_WritePin(nRF24_GPIO_CSn_port, nRF24_GPIO_CSn_pin, GPIO_PIN_RESET);
}
/*!
* \brief disable SPI, set CS HIGH.
*/
void nRF24_spi_disable() {
HAL_GPIO_WritePin(nRF24_GPIO_CSn_port, nRF24_GPIO_CSn_pin, GPIO_PIN_SET);
}
/*!
* \brief read nRF24L01 register
* \param REGISTER register address
* \param value read out data
* \param len read out bytes
* \return HAL_status
*/
uint8_t nRF24_read_REGISTER(uint8_t REGISTER, uint8_t *value, uint8_t len) {
uint8_t ret;
uint8_t status;
uint8_t cmd=R_REGISTER|REGISTER;
nRF24_spi_enable();
ret = HAL_SPI_TransmitReceive(nRF24_SPI, &cmd, &status,1 , nRF24_SPI_TIMEOUT);
if (ret == HAL_OK) {
ret = HAL_SPI_Receive(nRF24_SPI, value, len, nRF24_SPI_TIMEOUT);
}
nRF24_spi_disable();
return ret;
}
/*!
* \brief write data into nRF24L01 register
* \param REGISTER register address
* \param value write data
* \param len write bytes
* \return HAL status
*/
uint8_t nRF24_write_REGISTER(uint8_t REGISTER, uint8_t *value, uint8_t len) {
uint8_t ret;
uint8_t status;
uint8_t cmd =W_REGISTER | REGISTER;
nRF24_spi_enable();
ret = HAL_SPI_TransmitReceive(nRF24_SPI, &cmd, &status, 1, nRF24_SPI_TIMEOUT);
if (ret == HAL_OK) {
ret = HAL_SPI_Transmit(nRF24_SPI, value, len, nRF24_SPI_TIMEOUT);
}
nRF24_spi_disable(0);
return ret;
}
/*!
* \brief R_RX_PL_WIN: nRF24L01 received payload width
* \param width payload width
*/
uint8_t nRF24_get_RX_payload_width(uint8_t *width) {
uint8_t ret;
uint8_t status;
uint8_t cmd=R_RX_PL_WID;
nRF24_spi_enable();
ret = HAL_SPI_TransmitReceive(nRF24_SPI, &cmd, &status, 1, nRF24_SPI_TIMEOUT);
if (ret == HAL_OK) {
ret = HAL_SPI_Receive(nRF24_SPI, width, 1, nRF24_SPI_TIMEOUT);
}
nRF24_spi_disable();
return ret;
}
/*!
* \brief R_RX_PAYLOAD: received payload
* \param payload received payload
* \param len received number of bytes
* \return HAL status
*/
uint8_t nRF24_read_payload(uint8_t *payload, uint8_t len) {
uint8_t ret;
uint8_t status;
uint8_t cmd=R_RX_PAYLOAD;
nRF24_spi_enable();
ret = HAL_SPI_TransmitReceive(nRF24_SPI, &cmd, &status, 1, nRF24_SPI_TIMEOUT);
if (ret == HAL_OK) {
ret = HAL_SPI_Receive(nRF24_SPI, payload, len, nRF24_SPI_TIMEOUT);
}
nRF24_spi_disable();
return ret;
}
/*!
* \brief W_TX_PAYLOAD: write payload
* \param payload received payload
* \param len received number of bytes
* \return HAL status
*/
uint8_t nRF24_write_payload(uint8_t *payload, uint8_t len) {
uint8_t ret;
uint8_t status;
uint8_t cmd = W_TX_PAYLOAD;
nRF24_spi_enable();
ret = HAL_SPI_TransmitReceive(nRF24_SPI, &cmd, &status, 1, nRF24_SPI_TIMEOUT);
if (ret == HAL_OK) {
ret = HAL_SPI_Transmit(nRF24_SPI, payload, len, nRF24_SPI_TIMEOUT);
}
nRF24_spi_disable();
return ret;
}
/*!
* \brief W_TX_PAYLOAD_NOACK: write payload without acknowledgment. enable EN_DYN_ACK in FEATURE
* \param payload received payload
* \param len received number of bytes
* \return HAL staus
*/
uint8_t nRF24_write_payload_no_ack(uint8_t *payload, uint8_t len) {
uint8_t ret;
uint8_t status;
uint8_t cmd =W_TX_PAYLOAD_NOACK;
nRF24_spi_enable();
ret = HAL_SPI_TransmitReceive(nRF24_SPI, &cmd, &status, 1, nRF24_SPI_TIMEOUT);
if (ret == HAL_OK) {
ret = HAL_SPI_Transmit(nRF24_SPI, payload, len, nRF24_SPI_TIMEOUT);
}
nRF24_spi_disable();
return ret;
}
/*!
* \brief FLUSH RX FIFO
*/
uint8_t nRF24_flush_rx() {
uint8_t ret;
uint8_t cmd=FLUSH_RX;
uint8_t status;
nRF24_spi_enable();
ret = HAL_SPI_TransmitReceive(nRF24_SPI, &cmd, &status, 1, nRF24_SPI_TIMEOUT);
nRF24_spi_disable();
return ret;
}
/*!
* \brief FLUSH TX FIFO
*/
uint8_t nRF24_flush_tx() {
uint8_t ret;
uint8_t cmd=FLUSH_TX;
uint8_t status;
nRF24_spi_enable();
ret = HAL_SPI_TransmitReceive(nRF24_SPI, &cmd, &status, 1, nRF24_SPI_TIMEOUT);
nRF24_spi_disable();
return ret;
}
uint8_t nRF24_reuse_tx_pl() {
uint8_t ret;
uint8_t cmd=REUSE_TX_PL;
uint8_t status;
nRF24_spi_enable();
ret = HAL_SPI_TransmitReceive(nRF24_SPI, &cmd, &status, 1, nRF24_SPI_TIMEOUT);
nRF24_spi_disable();
return ret;
}
/*!
* \brief W_ACK_PAYLOAD
*/
uint8_t nRF24_write_ack_payload(uint8_t data_pipe, uint8_t *payload, uint8_t len) {
uint8_t ret;
uint8_t status;
uint8_t cmd=W_ACK_PAYLOAD | (data_pipe&0x07);
nRF24_spi_enable();
ret = HAL_SPI_TransmitReceive(nRF24_SPI, &cmd, &status, 1, nRF24_SPI_TIMEOUT);
if (ret == HAL_OK) {
ret = HAL_SPI_Transmit(nRF24_SPI, payload, len, nRF24_SPI_TIMEOUT);
}
nRF24_spi_disable();
return ret;
}
uint8_t nRF24_set_TX_addr(uint8_t *addr, uint8_t len) {
return (nRF24_write_REGISTER(TX_ADDR, addr, len));
}
uint8_t nRF24_get_TX_addr(uint8_t *addr, uint8_t len) {
return (nRF24_read_REGISTER(TX_ADDR, addr, len));
}
uint8_t nRF24_set_RX_addr(uint8_t data_pipe, uint8_t *addr, uint8_t len) {
uint8_t rx_addr_reg = RX_ADDR_P0 + data_pipe;
if (data_pipe > 1) len = 1;
return (nRF24_write_REGISTER(rx_addr_reg, addr, len));
}
uint8_t nRF24_get_RX_addr(uint8_t data_pipe, uint8_t *addr, uint8_t len) {
uint8_t rx_addr_reg = RX_ADDR_P0 + data_pipe;
if (data_pipe > 1) len = 1;
return (nRF24_read_REGISTER(rx_addr_reg, addr, len));
}
uint8_t nRF24_status(uint8_t *status) {
uint8_t ret;
uint8_t cmd = NOP;
nRF24_spi_enable();
ret = HAL_SPI_TransmitReceive(nRF24_SPI, &cmd, status, 1, nRF24_SPI_TIMEOUT);
nRF24_spi_disable();
return ret;
}
/*!
* \param channel 0~125
*/
uint8_t nRF24_set_RF_channel(uint8_t channel) {
if (channel > 125) channel = 125;
return (nRF24_write_REGISTER(RF_CH, &channel,1));
}
/*!
* \param pa: PA_0dBM, PA_m_6dBm(-6dBm), PA_m_12dBm, PA_m_18dBm
*/
uint8_t nRF24_set_power_amplifier(uint8_t pa) {
uint8_t rf_setup;
if(nRF24_read_REGISTER(RF_SETUP, &rf_setup,1) != HAL_OK) return HAL_ERROR;
rf_setup &= 0xF9;
switch(pa) {
case PA_0dBm:
rf_setup |= 0x06;
break;
case PA_m_6dBm:
rf_setup |= 0x04;
break;
case PA_m_12dBm:
rf_setup |= 0x02;
break;
case PA_m_18dBm:
rf_setup |= 0x00;
break;
}
return (nRF24_write_REGISTER(RF_SETUP, &rf_setup,1));
}
/*!
* \param aw 3~5
*/
uint8_t nRF24_set_address_width(uint8_t aw) {
if (aw >=3 && aw <= 5 ) {
aw -= 2;
return (nRF24_write_REGISTER(SETUP_AW, &aw,1));
}
else
return HAL_ERROR;
}
uint8_t nRF24_get_address_width(uint8_t *aw) {
if (nRF24_read_REGISTER(SETUP_AW, aw,1) != HAL_OK) {
*aw=0;
return HAL_ERROR;
}
*aw = *aw+2;
return HAL_OK;
}
/*!
* \brief EN_AA register
*/
uint8_t nRF24_enable_auto_ack(uint8_t data_pipe, uint8_t enable) {
uint8_t aa;
uint8_t mask;
if (data_pipe < 0 || data_pipe > 5) return HAL_ERROR;
mask = 0x1 << data_pipe;
if(nRF24_read_REGISTER(EN_AA, &aa, 1) != HAL_OK) return HAL_ERROR;
if (enable) {
aa |= mask;
} else {
aa &= (mask^0xFF);
}
return (nRF24_write_REGISTER(EN_AA, &aa,1));
}
/*!
* \param feature FEATURE_EN_DYN_ACK, FEATURE_EN_ACK_PAY, FEATURE_EN_DPL
* \param enable true:enable, false:disable
*/
uint8_t nRF24_enable_feature(uint8_t feature, uint8_t enable) {
uint8_t buff;
if(nRF24_read_REGISTER(FEATURE, &buff, 1) != HAL_OK) return HAL_ERROR;
if (enable) {
buff |= (0x01 << feature);
} else {
buff &= ((0x01 << feature) ^ 0xFF);
}
return (nRF24_write_REGISTER(FEATURE, &buff,1));
}
/*!
* \brief DYNPD register
*/
uint8_t nRF24_enable_data_pipe_dynamic_payload_length(uint8_t data_pipe, uint8_t enable) {
if (data_pipe < 0 || data_pipe > 5) return HAL_ERROR;
if (nRF24_enable_feature(FEATURE_EN_DPL, 1) != HAL_OK) return HAL_ERROR;
if (nRF24_enable_auto_ack(data_pipe, 1) != HAL_OK) return HAL_ERROR;
uint8_t dynpd;
uint8_t mask;
mask = 0x1 << data_pipe;
if(nRF24_read_REGISTER(DYNPD, &dynpd, 1) != HAL_OK) return HAL_ERROR;
if (enable) {
dynpd |= mask;
} else {
dynpd &= (mask^0xff);
}
return (nRF24_write_REGISTER(DYNPD, &dynpd,1));
}
/*!
* \brief Received Power Detector (RPD)
*/
uint8_t nRF24_get_RPD(uint8_t *rpd_value) {
return (nRF24_read_REGISTER(RPD, rpd_value, 1));
}
/*!
* \brief RX_PW_Px register, Number of bytes in RX payload in data pipe Px
*/
uint8_t nRF24_set_recv_payload_width(uint8_t data_pipe, uint8_t width) {
if (width > 32 || width < 0) return HAL_ERROR;
uint8_t rx_pw_px = RX_PW_P0+data_pipe;
return (nRF24_write_REGISTER(rx_pw_px, &width, 1));
}
/*!
* \brief enable RX Address at data pipe x
* \param mask 0b00xxxxxx: ex. 0b00010111 enable p0~2 & p4
*/
uint8_t nRF24_enable_RXADDR(uint8_t mask) {
return (nRF24_write_REGISTER(EN_RXADDR, &mask, 1));
}
uint8_t nRF24_set_data_rate(uint8_t rate) {
uint8_t rf_setup;
if(nRF24_read_REGISTER(RF_SETUP, &rf_setup, 1) != HAL_OK) return HAL_ERROR;
rf_setup &= 0xD7;
switch(rate) {
case DATA_RATE_250K:
rf_setup |= 0x20;
break;
case DATA_RATE_1M:
rf_setup |= 0x00;
break;
case DATA_RATE_2M:
rf_setup |= 0x08;
break;
}
return (nRF24_write_REGISTER(RF_SETUP, &rf_setup,1));
}
/*!
* \brief set nRF24L01+ mode
* \param PRIM_RX 1:PRX, 0: PTX
* \return HAL status
*/
uint8_t nRF24_config_mode(uint8_t PRIM_RX) {
uint8_t ret;
uint8_t mode;
ret = nRF24_read_REGISTER(CONFIG, &mode, 1);
if (ret == HAL_OK) {
nRF24_disable_CE();
HAL_Delay(1);
mode = (mode & 0xFE) | (PRIM_RX & 0x01);
ret = nRF24_write_REGISTER(CONFIG, &mode,1);
nRF24_enable_CE();
HAL_Delay(1);
}
return ret;
}
/*!
* \param irq_type EVENT_MAX_RT, EVENT_TX_DS, EVENT_RX_DR
* \param enable
*/
uint8_t nRF24_enable_IRQ(uint8_t irq_type, uint8_t enable) {
if (irq_type < EVENT_MAX_RT || irq_type > EVENT_RX_DR) return HAL_ERROR;
uint8_t config;
uint8_t mask=0x01 << irq_type;
if (nRF24_read_REGISTER(CONFIG, &config, 1) != HAL_OK) return HAL_ERROR;
if (enable) {
config &= (mask ^ 0xFF);
} else {
config |= mask;
}
return nRF24_write_REGISTER(CONFIG, &config, 1);
}
/*!
* \brief clear MAX_RT interrupt
*/
uint8_t nRF24_clear_MAX_RT() {
uint8_t status;
if (nRF24_status(&status) != HAL_OK) return HAL_ERROR;
if (status & 0x10) {
status |= 0x10;
return (nRF24_write_REGISTER(STATUS, &status, 1));
}
return HAL_ERROR;
}
/*!
* \brief clear TX_DS interrupt
*/
uint8_t nRF24_clear_TX_DS() {
uint8_t status;
if (nRF24_status(&status)!=HAL_OK) return HAL_ERROR;
if (status & 0x20) {
status |= 0x20;
return (nRF24_write_REGISTER(STATUS, &status, 1));
}
return HAL_ERROR;
}
/*!
* \brief clear RX_DR interrupt
*/
uint8_t nRF24_clear_RX_DR() {
uint8_t status;
if (nRF24_status(&status) != HAL_OK) return HAL_ERROR;
if (status & 0x40) {
status |= 0x40;
return (nRF24_write_REGISTER(STATUS, &status, 1));
}
return HAL_ERROR;
}
static void nRF24_standby_to_txrx_mode(){
nRF24_enable_CE();
//busy_wait_us(140); // Standby modes --> TX/RX mode : max 130us.
// Delay from CE positive edge to CSN low : min 4us
HAL_Delay(1);
}
/*!
* \brief set SETUP_RETR register bit 7:4 Auto Retransmit Delay
* \param delay time = 250us*(delay+1), value:0x00~0x0f
*/
uint8_t nRF24_set_auto_retransmit_delay(uint8_t delay) {
uint8_t ard;
if (delay > 0x0f) delay = 0x0f;
if (nRF24_read_REGISTER(SETUP_RETR, &ard,1) == HAL_OK) {
ard = (ard&0x0f) | delay << 4;
return (nRF24_write_REGISTER(SETUP_RETR, &ard, 1));
}
return HAL_ERROR;
}
uint8_t nRF24_fifo_tx_full(uint8_t *full) {
uint8_t fifo_status;
uint8_t ret;
ret = nRF24_read_REGISTER(FIFO_STATUS, &fifo_status, 1);
if (ret == HAL_OK) {
fifo_status &= 0x20;
*full = fifo_status >> 5;
}
return ret;
}
uint8_t nRF24_fifo_tx_empty(uint8_t *empty) {
uint8_t fifo_status;
uint8_t ret;
ret = nRF24_read_REGISTER(FIFO_STATUS, &fifo_status, 1);
if (ret == HAL_OK) {
fifo_status &= 0x10;
*empty = fifo_status >> 4;
}
return ret;
}
uint8_t nRF24_fifo_rx_full(uint8_t *full) {
uint8_t fifo_status;
uint8_t ret;
ret = nRF24_read_REGISTER(FIFO_STATUS, &fifo_status, 1);
if (ret == HAL_OK) {
fifo_status &= 0x02;
*full = fifo_status >> 1;
}
return ret;
}
uint8_t nRF24_fifo_rx_empty(uint8_t *empty) {
uint8_t fifo_status;
uint8_t ret;
ret = nRF24_read_REGISTER(FIFO_STATUS, &fifo_status, 1);
if (ret == HAL_OK) {
fifo_status &= 0x01;
*empty = fifo_status;
}
return ret;
}
static void nRF24_reset_REGISTER() {
uint8_t value;
value=0x3f;
nRF24_write_REGISTER(EN_AA, &value, 1);
value=0x0a;
nRF24_write_REGISTER(CONFIG, &value, 1);
value=0x03;
nRF24_write_REGISTER(EN_RXADDR, &value, 1);
value=0x03;
nRF24_write_REGISTER(SETUP_AW, &value, 1);
value=0x03;
nRF24_write_REGISTER(SETUP_RETR, &value, 1);
value=0x02;
nRF24_write_REGISTER(RF_CH, &value, 1);
value=0x0f;
nRF24_write_REGISTER(RF_SETUP, &value, 1);
nRF24_flush_rx(); //reset STATUS
nRF24_flush_tx();
value=0x0e;
nRF24_write_REGISTER(STATUS, &value, 1);
value=0x00;
nRF24_write_REGISTER(RX_PW_P0, &value, 1);
nRF24_write_REGISTER(RX_PW_P1, &value, 1);
nRF24_write_REGISTER(RX_PW_P2, &value, 1);
nRF24_write_REGISTER(RX_PW_P3, &value, 1);
nRF24_write_REGISTER(RX_PW_P4, &value, 1);
nRF24_write_REGISTER(RX_PW_P5, &value, 1);
nRF24_write_REGISTER(DYNPD, &value, 1);
nRF24_write_REGISTER(FEATURE, &value, 1);
}
/*!
* \brief HAL_GPIO_EXTI_Callback used by nRF24L01 driver. User must define nRF24_irq_callback
* to get interrupt event
* \param event_type EVENT_RX_DR: Receiver Data Ready,
* EVENT_TX_DS: Transmitter Data Sent,
* EVENT_MAX_RT:Transmitter retransmit
* EVENT_GPIO_IRQ: gpio interrupt handler except nRF24L01 IRQ GPIO_pin
* \param data_src nRF24L01 datapipe or GPIO_pin
* \param data nRF24L01 received data
* \param width nRF24L01 received data length
*/
__weak void nRF24_irq_callback(uint8_t event_type, uint16_t data_src, uint8_t* data, uint8_t width) {
switch(event_type) {
case EVENT_RX_DR:
break;
case EVENT_TX_DS:
break;
case EVENT_MAX_RT:
break;
case EVENT_GPIO_IRQ:
break;
}
} #ifndef __nRF24L01_H__
#define __nRF24L01_H__
// Command
#define R_REGISTER 0b00000000
#define W_REGISTER 0b00100000
#define R_RX_PAYLOAD 0b01100001
#define W_TX_PAYLOAD 0b10100000
#define FLUSH_TX 0b11100001
#define FLUSH_RX 0b11100010
#define REUSE_TX_PL 0b11100011
#define ACTIVATE 0b01010000 //nRF24L01 Product Specification
#define R_RX_PL_WID 0b01100000
#define W_ACK_PAYLOAD 0b10101000 // 0b10100PPP
#define W_TX_PAYLOAD_NOACK 0b10110000
#define NOP 0b11111111
//Registers
#define CONFIG 0x00
#define EN_AA 0x01
#define EN_RXADDR 0x02
#define SETUP_AW 0x03
#define SETUP_RETR 0x04
#define RF_CH 0x05
#define RF_SETUP 0x06
#define STATUS 0x07
#define OBSERVE_TX 0x08
#define RPD 0x09
#define RX_ADDR_P0 0x0A
#define RX_ADDR_P1 0x0B
#define RX_ADDR_P2 0x0C
#define RX_ADDR_P3 0x0D
#define RX_ADDR_P4 0x0E
#define RX_ADDR_P5 0x0F
#define TX_ADDR 0x10
#define RX_PW_P0 0x11
#define RX_PW_P1 0x12
#define RX_PW_P2 0x13
#define RX_PW_P3 0x14
#define RX_PW_P4 0x15
#define RX_PW_P5 0x16
#define FIFO_STATUS 0x17
#define DYNPD 0x1C
#define FEATURE 0x1D
#define TRANSMITTER 0
#define RECEIVER 1
typedef enum {
DATA_RATE_250K=0,
DATA_RATE_1M,
DATA_RATE_2M
} nRF24_DATA_RATE;
typedef enum {
PA_0dBm=0,
PA_m_6dBm,
PA_m_12dBm,
PA_m_18dBm,
} nRF24_PA;
typedef enum {
AW_3=1,
AW_4,
AW_5,
} nRF24_ADDRESS_WIDTH;
typedef enum {
FEATURE_EN_DYN_ACK=0, // W_TX_PAYLOAD_NOACK
FEATURE_EN_ACK_PAY,
FEATURE_EN_DPL,
}nRF24_FEATURE_MASK;
typedef enum {
EVENT_MAX_RT=4,
EVENT_TX_DS,
EVENT_RX_DR,
EVENT_GPIO_IRQ,
} nRF24_IRQ_EVENT;
//typedef void (*nRF24_irq_callback_t)(uint8_t evant_type, uint16_t data_src, uint8_t* data, uint8_t width);
void nRF24_spi_init(SPI_HandleTypeDef* spi,GPIO_TypeDef* csn_port, uint32_t csn_pin, GPIO_TypeDef* ce_port, uint32_t ce_pin, GPIO_TypeDef* irq_port, uint32_t irq_pin);
uint8_t nRF24_status(uint8_t *status);
uint8_t nRF24_read_REGISTER(uint8_t REGISTER, uint8_t *value, uint8_t len);
uint8_t nRF24_write_REGISTER(uint8_t REGISTER, uint8_t *value, uint8_t len);
uint8_t nRF24_config_mode(uint8_t PRIM_RX);
uint8_t nRF24_set_data_rate(uint8_t rate);
uint8_t nRF24_set_RF_channel(uint8_t channel);
uint8_t nRF24_set_power_amplifier(uint8_t pa);
uint8_t nRF24_set_address_width(uint8_t aw);
uint8_t nRF24_set_auto_retransmit_delay(uint8_t delay);
uint8_t nRF24_set_recv_payload_width(uint8_t data_pipe, uint8_t width);
uint8_t nRF24_set_RX_addr(uint8_t data_pipe, uint8_t *addr, uint8_t len);
uint8_t nRF24_set_TX_addr(uint8_t *addr, uint8_t len);
uint8_t nRF24_get_RPD(uint8_t *rpd_value);
uint8_t nRF24_get_RX_payload_width(uint8_t *width);
uint8_t nRF24_get_address_width(uint8_t *aw);
uint8_t nRF24_get_auto_retransmit_delay(uint8_t *delay);
uint8_t nRF24_get_RX_addr(uint8_t data_pipe, uint8_t *addr, uint8_t len);
uint8_t nRF24_get_TX_addr(uint8_t *addr, uint8_t len);
uint8_t nRF24_enable_auto_ack(uint8_t data_pipe, uint8_t enable);
uint8_t nRF24_enable_data_pipe_dynamic_payload_length(uint8_t data_pipe, uint8_t enable);
uint8_t nRF24_enable_feature(uint8_t feature, uint8_t enable);
uint8_t nRF24_enable_RXADDR(uint8_t mask);
uint8_t nRF24_read_payload(uint8_t *payload, uint8_t len);
uint8_t nRF24_write_payload(uint8_t *payload, uint8_t len);
uint8_t nRF24_write_payload_no_ack(uint8_t *payload, uint8_t len);
uint8_t nRF24_flush_rx();
uint8_t nRF24_flush_tx();
uint8_t nRF24_reuse_tx_pl();
uint8_t nRF24_write_ack_payload(uint8_t data_pipe, uint8_t *payload, uint8_t len);
uint8_t nRF24_clear_MAX_RT();
uint8_t nRF24_clear_TX_DS();
uint8_t nRF24_clear_RX_DR();
uint8_t nRF24_fifo_tx_full(uint8_t *full);
uint8_t nRF24_fifo_rx_full(uint8_t *full);
uint8_t nRF24_fifo_tx_empty(uint8_t *empty);
uint8_t nRF24_fifo_rx_empty(uint8_t *empty);
void nRF24_irq_callback(uint8_t event_type, uint16_t data_src, uint8_t* data, uint8_t width);
#endif
